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February 8 1996

Hitachi, Ltd. and Mitsubishi Electric Corp. have jointly developed a 64-Mbit AND-type flash memory with a high-speed 50-ns serial access time (read time)*1 from a single 3.3-V power supply and data erasure in 512-byte units.

Flash memory is a nonvolatile memory that allows data to be rewritten electrically. Unlike volatile memory technologies, such as DRAM*2 and SRAM*3, data is not lost when the power is turned off. Since battery backup for data retention is therefore not required, flash memory reduces the power requirement and allows greater miniaturization.

The main applications for flash memory include storing codes in portable telephones, and for large-capacity products, data storage in still cameras and external storage for personal computers, such as PC card memory. With the expansion of the multimedia market, demand for flash memory is expected to grow rapidly, and 64-Mbit class flash memory products are particularly important as external storage for computers. When flash memory is mounted either internally or on memory cards, memory systems can be built that are more compact and have lower power requirements than hard disk systems. For such applications, high- speed access, high-speed rewriting, and even lower power requirements are desired in 64-Mbit flash memory devices.

Conventional flash memory products are mostly based on one of two technologies: the so-called NOR type*4 and the NAND type*5. The NOR type can provide a high-speed read operation of about 100 ns, but its memory cell size is about twice that of the NAND type, making high integration densities difficult to achieve. Furthermore, since the CHE method*6 used for writing to the memory cells draws a relatively large current, an external high- voltage power supply is required. The NAND type, on the other hand, allows high integration densities, supports high-speed serial access, and can run on a single power supply. However, the NAND type suffers from the problem that data must be erased in large units that are not the same size as the units in which data is written.

The AND type cell developed for this flash memory device also allows high integration densities, supports high-speed serial access, and can run on a single power supply. Since a tunneling scheme*7, which does not require a large current, is used for writing cells, this flash memory device allows the high voltage required for rewriting to be generated on the chip, so the chip can run on a single 3.3-V power supply. This flash memory uses a serial access method and offers a 50-ns high-speed serial access (read time).

The array structure in this device is organized hierarchically in which the bit line is divided into a main bit line and subsidiary bit lines. Each memory cell is connected to the subsidiary bit lines in parallel. This allows data to be erased in word line units, hence the device can erase data in units as small as 512 bytes for high-speed data rewriting.

In addition to the above features, this flash memory also provides a status polling function, a delete function, and an automatic page write function that automatically performs the complex algorithms for writing and deleting when simple commands are issued. The device also has a 16-byte management area for deleting individual units (pages). These functions simplify the data writing and management operations, and thus make it easier to develop the system software.

The device is fabricated using a 0.4-micron CMOS process.

In January 1994, Hitachi and Mitsubishi Electric Corp. agreed in principle on the co-development of flash memories utilizing the new technologies of DINOR*8 and AND. Under the agreement, the companies will jointly develop a 16-Mbit flash memory based on the DINOR cell structure technology provided by Mitsubishi and a 64-Mbit flash memory based on the AND cell structure technology provided by Hitachi.

This 64-Mbit flash memory is the second device jointly developed under this agreement. Hitachi and Mitsubishi will be presenting this architecture on February 8, 1996, at the International Solid State Circuit Conference, in the US.

*1 Serial access: An access technique in which data is read out sequentially in larger units.
*2 DRAM: Dynamic random access memory
*3 SRAM: Static random access memory
*4 NOR type: The flash memory technology used by Intel Corporation and most other producers. The name derives from the fact that the cells are connected in parallel relative to the bit lines.
*5 NAND type: Proposed by Toshiba Corporation. The name derives from the fact that the cells are connected in series relative to the bit lines.
*6 CHE method: Channel Hot Electron. This is a write technique in which a high voltage is applied between the gate and the drain to increase the energy of the electrons that pass through the channel. These electrons are inserted into a floating gate. This method requires a large current.
*7 Tunneling scheme: Techniques that use a phenomenon in which electrons pass through a thin oxide film due to an electric field applied across the film.
*8 DINOR: Divided bit-line NOR

Features:

1. Single 3.3-V power supply

This device performs read and write operations in a 64-Mbit large-capacity flash memory device with a single 3.3-V power supply. This makes system and board design easier, and reduces the system power requirements.

2. High-speed serial access

This flash memory features a 50-ns high-speed serial access for improved system performance.

3. Erasure in 512-byte units

Since the unit of erasure is small and is the same size as the unit of writing, the device erases only the data that needs to be rewritten. This simplifies the write management and operations on the system side.

Examples of Product Applications:

- Image memory for digital cameras
- Auxiliary storage for palmtop and notebook personal computers