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17 October 1996

Hitachi, Ltd. announced it is releasing the Quick Series (Q Series) of graphics accelerators(*1) that will enable graphics processing for car navigation systems, Internet TVs, and other consumer information products, to be executed at high speed by compact systems, and improve the representational capabilities of such systems. Use of a Q Series device in a chip set including a Hitachi 32-bit RISC microcomputer "SuperH RISC engine family" (SuperH family) will enable the geometrical processing,(*2) rendering processing,(*3) and display processing required by a graphic display system to be implemented at high speed in a compact system. Based on the design concepts of simplicity, real- time capability, and upgradability, the Q Series performs rendering and display processing tailored to the SuperH family. The first product in the new series is the " HD 64411" Quick 2D Graphics Renderer (Q2), a 2D graphics rendering chip that enables graphics memory size to be cut by more than 50%, and is also capable of 3D-like graphics display. Sample shipments will begin in October 1996 in Japan.

Today's home game systems offer a high level of both display responsiveness and representational capability in the implementation of their man-machine interface. The release of low-priced game machines has also raised hopes of a dramatic improvement in graphic display capability in the entire consumer information device market, including car navigation systems and Internet TVs. In addition to the need for high processing performance and simplicity of implementation, there is also a growing demand for upward-compatibility of software and data bases, and concern over how to handle increasingly complex graphics algorithms.

The approach to meeting these requirements in conventional graphic display systems has been to use a CPU, which executes the geometrical processing and rendering processing by using large amounts of high-speed memory, or to use an embedded graphics chip, which executes graphics algorithms as far as possible at the relevant points in time. However, users are now looking for a configuration in which geometrical processing is executed by the CPU and rendering processing by dedicated hardware, and the demand is for a chip set which combining a microcomputer with an LSI to handle rendering and display processing. In response to this demand, Hitachi developed the Q Series of graphics accelerators to perform high-speed rendering and display processing as a chip set together with the SuperH family, which executes the geometrical processing. A Q Series LSI is designed around the concepts of simplicity, real-time capability, and upgradability.

Hitachi has been involved in the development of various display control chips for some time, and is currently mass- producing the HD64400 GDP (Graphics Data Processor) for high-speed graphics and image processing, and the HD64410 ARTOP (Art Operating Processor) with built-in high-speed graphics processing and programming functions. Based on these high-speed graphics technologies, Hitachi has now developed, as the first product in its Q Series, the HD64411 (Q2) 2D graphics rendering chip, which enables external graphics memory to be reduced by more than 50% and also offers 3D-like graphics display capability.

The Q2 incorporates high-speed 2D drawing functions plus high-performance rendering functions with the addition of texture mapping for effective 3D graphics processing by software, as well as the SuperH family interface functions, memory interface and display control functions. For example, using a 25x20-dot rectangle, the Q2 can draw 15,000 polygons (*4) per second (at 16 bits per pixel).

The graphics memory management method used by the Q2 is the Unified-Graphics-Memory Architecture.(*5) In contrast to a conventional ARTOP found in previous Hitachi products, which differentiates between color graphics for natural images, etc., from data with a different data format, such as fonts and patterns, the Q2 can handle all graphic data in the same memory. And the use of cost-efficient EDO (Extended Data Output) DRAM for the frame buffer (video display memory) makes it possible to configure a system with a single 4M-bit EDO DRAM, where 16Mbits or more of high-speed DRAM was previously required, further reducing system cost.

Moreover, four carefully selected commands, including a 4-vertex polygon drawing command that allows free transformation of natural and graphical images, enable 2D graphics to be implemented at high speed, and also make 3D-like graphics display possible. This kind of graphics processing is implemented with a drawing speed 13 times that of a conventional ARTOP, thanks to an increase in the operating frequency to 33MHz and a reduction of the number of processing cycles per pixel from 17 to 3. Furthermore, the Q2 implements real-time drawing through the use of a double-buffer architecture.(*6) Continuity between current and future systems is also facilitated by such basic functions as direct DRAM connection, TV-synchronized display, sync signal generation, built-in color palette, and color space conversion (YUV->RGB, RGB-> YCrCb).

These features enable a wide range of multimedia terminal graphics processing systems-including medium-definition OA products, such as, car navigation systems and network computers, industrial equipment display systems, Internet TVs, and Karaoke systems-to be implemented in compact form and with a high level of drawing performance. The Q2 uses a 0.6 micron 2-layer aluminum CMOS process, and is mounted on a 144-pin QFP plastic board, enabling a high-performance display system to be configured at low cost. Future development plans include a 66MHz version in addition to the present 33 MHz version.

[Notes]

1. Accelerator: A chip that assists microcomputer operation by providing mechanisms for shortening processing time.

2. Geometrical processing: Processing the numeric values in coordinate conversion, including vertex parallel shifting and rotation processing.

3. Rendering processing: Processing that draws lines and surfaces in graphics memory to represent the target figure.

4. Polygon: A graphic unit used in expressing drawing processing time. The size of one unit varies depending on the graphic. For example, in the case of a surface, a rectangular area of 20x25 pixels is taken as a single-unit polygon, and the polygon index indicates how many polygons of this size can be processed per unit time.

5. Unified-Graphics-Memory Architecture: A method of managing data of different formats in the same memory. Data of different formats includes natural images and other color graphics, font patterns, display strings (drawing command strings), and figures created by drawing.

6. Double-buffer architecture: An architecture in which two areas-one used for drawing and one for display-are provided in graphics memory, and their roles are switched at regular intervals. This architecture enables display processing and rendering processing to be carried out in intersecting fashion.

[Typical Applications]

- Small-screen OA products (network computers, etc.)
- Car navigation systems
- AV products (Internet TVs, Karaoke systems)
- Industrial equipment display systems

[Pricing in Japan] (Provided for reference purpose only)

Product Code	Sample Price (Yen)
HD64411	3000

[Features]

1. Enables implementation of compact, high-speed graphic display systems as a chip set together with a SuperH family. The Q2 is provided with high-performance rendering functions with the addition of texture mapping, enabling 3-D graphics like display. A SuperH family interface function, memory interface, and display control functions are also included on-chip.

2. Unified o Graphics o Memory Architecture
A system previously configured using at least 16 Mbits of high-speed RAM can be implemented with 4-Mbit EDO DRAM, cutting thesize of graphics memory by more than 50%.

3. Double-buffer architecture
Enables execution of real-time drawing.

4. High-speed drawing
Improvements such as raising the operating frequency to 33 MHz have resulted in a 13-fold increase in drawing speed compared with Hitachi's previous ARTOP product.

[Specifications]