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March 6,1997

Hitachi Releases SH7410 as the First Product of SH-DSP Combining 32-Bit RISC Microcomputer and DSP

- 60 MIPS RISC processor performance and 120 MOPS DSP performance achieved with small core size -

The SuperH(TM)(*2) RISC engine family of 32-bit RISC microcomputers offers a high level of control thanks to its RISC architecture and also incorporates a multiplier that executes multiply-and-accumulate operations, enabling digital signal processing of, for example, voice data, image data, and servo control, to be carried out at high speed. However communications and multimedia applications such as digital cellular phones and digital still cameras, that handle large volumes of compressed voice and image data in real time, require a two-chip system configuration of a RISC, such as the existing SuperH, and a DSP capable of performing multiply-and-accumulate operations in one cycle. With this kind of system there was a need for further size reduction to improve portability. From the software design standpoint, too, there was the problem of the use of different programming languages in the RISC processor and the DSP because of the enormous time and skill requirements for program writing.

Against this background, and to enable systems to be made smaller and both hardware and software design to be simplified in fields requiring sophisticated system control and high-level digital signal processing performance, Hitachi developed the SH7410 (HD6437410F), which combines a RISC processor and a DSP on a level with a general-purpose model in a single chip with a small core size.

This product is fabricated by a 0.35-micron Al 3 layer process and has 8kB RAM and 48kB ROM. It performs system control at a high-performance level of 60 MIPS at 3 V. To improve DSP performance, the number of internal buses has been increased from one to three through the use of a Harvard architecture, enabling multiply-and-accumulate operations to be executed in one cycle instead of the previous three cycles. This has resulted in a digital signal processing performance of 120 MOPS, equivalent to that of a 60 MHz general-purpose DSP. The SH7410 incorporates DSP parallel instructions, no-overhead repeat instructions and a modulo address function essential for a DSP. When used in a digital still camera, the SH7410 can perform high-speed JPEG processing by means of software only-for example, compressing a 640 x 480 VGA(*3) screen in only 0.36 second (at Y:Cr:Cb= 4:1:1). And ADPCM voice compression--the key technology in PHS portable terminals--can be accomplished at 10 MIPS (1/6 of the SH7410's 60 MIPS capability) by means of the DSP functions, allowing the remaining capacity to be used to implement telecommunication control or other functions. The SH7410 outperforms the previous SuperH by approximately 2 to 3 times in signal processing program applications that push DSP to the limit, while also providing the flexibility needed to achieve the best balance between CPU and DSP performance utilization for the performance of the equipment.

In these SH-DSP chips, the CPU core and DSP core are merged, eliminating duplicate circuits and functions, and achieving a small core size. Moreover, software design is speeded up and simplified since the same program can be used for both cores. The instruction set is fully upward-compatible with the SH-1 and SH-2, enabling current SuperH users to make use of their existing software resources while adding high-level DSP capability. The SH7410 is mounted in a 176-pin LQFP package. As system support, Hitachi provides development cross software, an "E8000" emulator and an emulator incorporating a serial interface conforming to the JTAG interface standard, "E10". Additionally, Hitachi will provide 41 kinds of DSP libraries as part of SuperH C program, and application software (middleware).

Future plans for the SH-DSP include extending the memory lineup to a cache version and a flash version. Hitachi will also develop enhanced SH-DSP instructions and more comprehensive peripheral functions in line with market demand. For the SuperH family, there are plans for the development of a version with on-chip flash memory lineup and an SH-4 model with a superscalar CPU configuration and a target performance of 300 MIPS.

Notes:
*1 MOPS: Mega Operation Per Second
*2 SuperH: SuperH is a trade mark of Hitachi, Ltd.
*3 VGA: Video Graphics Array. A standard of graphics display used by IBM Corporation in its PCs

Application Examples

• Communications Equipment


• PHS (voice compression/decompression, channel codec, protocol control, system control)


• Digital cellular phones (voice compression/decompression, channel codec, protocol control, system control)


• Modems (modulation/demodulation, channel codec, protocol control, system control)


• Consumer


• Digital still cameras (high-speed software JPEG image compression, system control)


• Electronic musical instruments (PCM sound source, effector, system control)


• Multimedia products (voice/image compression/decompression, voice response/recognition, system control)


• Digital audio broadcasting (OFDM modulation, MPEG audio decoding)


• Information/OA Equipment


• Fax equipment (fax image compression, modem, system control)


• HDD (high-speed servo control, system control)


• PDA (voice/image compression/decompression, voice response/recognition, communications, system control)


• Industrial/Automotive


• Factory automation, numerical control (sequencing, servo control)


• Car navigation systems (voice recognition/response functions, addition of high-definition still picture display function, etc.)


• Automotive applications (knocking control, active suspension, noise cancellation)

Pricing in Japan

Product Name	Price in 10,000
HD6437410F	2,500 yen

Features

1. Single-chip microcomputer combining RISC microcomputer and DSP
- 60 MIPS system control and 120 MOPS high-speed processing at 60 MHz achieved through use of three-bus configuration and single-cycle multiply-and-accumulate operations
- Addition of DSP parallel instructions and DSP functions (repeat, modulo, etc.)

2. Mixed RISC/DSP program (Single instruction stream), and instruction set fully upward-compatible with SH-1 and SH-2
- Highly efficient RISC/DSP program development is possible with a single software development environment.
- Existing SuperH software resources can be used, and DSP functions can be added easily.
- Highly efficient software development is possible with C compiler. Digital signal processing will be incorporated more easily by signal processing libraries and middleware.

3. Single-chip implementation with small core size
Elimination of duplicated RISC microcomputer and DSP circuits and functions enables single-chip implementation with a small core size of 4 square millimeters.

4. Powerful on-chip peripheral functions
The SH7410 microcomputers incorporate the following powerful peripheral functions which are needed in digital still cameras and communications equipment such as cellular phones.
- 4-channel DMAC
- 3-channel 16-bit timer
- 2-channel serial communication interface (UART)
- 3-channel synchronous serial interface
- 32-bit I/O port
- Direct connection to external memory (DRAM, EDO, burst ROM, pseudo-SRAM, etc.)

5. High-speed on-chip debugging functions
- 2-channel break controller
- Serial debug interface conforming to JTAG interface standard

Specification

Item	HD6437410F
Process	0.35-micron, 3 Al layers
Power-supply voltage	2.7 to 3.6 V
Operating frequency	60 MHz
Processing speed	CPU: 60 MIPS DSP: 120 MOPS
CPU core	32-bit SH-RISC core, incorporating extended DSP function
	CPU: 32-bit general register x16 DSP: 32-bit data register x6, 40-bit data register x2, 64-bit MAC register
Number of CPU instructions	16-bit instructions: 62 instructions Fully upwards compatible with the SH-1 and SH-2)
Number of DSP instruction	16-bit instructions: 8 instructions
	32-bit instructions: 4 instructions (data transfer) x 21 instructions (data operation) = 84 parallel instructions
DSP multiply and accumulate function	16 bits x 16 bits + 40 bits --> 40 bits: One cycle
	16 bits x 16 bits --> 32 bits: One cycle
	32 bits x 32 bits + 64 bits --> 64 bits: 2 to 4 cycles
	32 bits x 32 bits --> 64 bits: 2 to 4 cycles
DSP functions	Parallel execution of data transfer and arithmetic instructions (up to 4 instructions executed in parallel)
	DSP instruction support for multiplication, addition, logical operations and shifting
	Saturation instructions
	Conditional branch instructions
	No-overhead iteration instruction
	Modulo addressing
Internal RAM	8 kB
Internal ROM	48 kB
External memory	Supports direct connection to DRAM, EDO DRAM, pseudo-SRAM, burst ROM, and other memory types
	Four 16-MB areas
	The number of wait cycles and the number of idle cycles used to prevent bus collisions can be set.
	Data bus width: 8, 16, or 32 bits
Built-in peripheral functions	Four-channel DMA
	Two-channel serial communications interface (UART)
	Three-channel serial interface
	Three-channel 16-bit free-running timer
	Interrupt controller
	32-bit parallel I/O port
	Clock generator : frequency-multiplier PLL built in
Built-in debugging functions	2-channel break controller
	Serial debug interface conforming to JTAG interface standard
	4-level PC branch trace FIFO
Package	LQFP176
	0.5-mm pitch
	24 mm x 24 mm

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