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September 24, 1997

Hitachi Releases 100 MIPS SH7708R and SH7718R as Top-End Models in 32-Bit SH-3 RISC Microprocessor Series

- High-performance/Low-power-consumption SH7708R, and SH7718R with additional floating-point functions, for portable information devices and multimedia products -

The SH-3 (SH7700 series) RISC microprocessors are designed to offer the high performance and low power consumption required in portable information devices and multimedia products within Hitachi's 32-bit SuperH(TM)(1) RISC engine family. Since their release in March 1995, the 60 MIPS SH 7708 and 45 MIPS SH7702 have come into wide use in line with the rapid growth of the multimedia market, including products such as portable information terminals, car navigation systems, and digital cameras. A further stimulus to this market was the release last year of Microsoft Corporation's new Windows(R) CE(2) operating system, which brought an improvement in the ease of use of such portable information devices and multimedia products. The SH7708 is compatible with Windows(R) CE, incorporates a memory management unit (MMU) for operating system support, and includes power management functions for fine control of power consumption. Hitachi has previously released the 60 MIPS SH7708S offering lower power consumption than that of SH7708, together with the 80 MIPS SH7709 as an enhanced version of the SH-3 (SH 7708), to meet the needs of a variety of user applications.

The newly developed SH7708R and SH7718R feature a 100 MIPS performance at 100 MHz operating frequency, and are equipped with an 8K byte on-chip cache. Like the SH7708, they use 16-bit fixed-length instructions for high code efficiency, enabling system ROM capacity to be minimized. The ability to switch the ratio between the bus frequency, CPU frequency, and on-chip supporting function frequency dynamically within a program (by means of control register settings), together with the provision of sophisticated power management functions including sleep, standby, and module stop modes, makes it possible to implement precise power management tuned to the operating mode of the application system. Also, these products include a 3x frequency multiplier for the CPU clock. Through the use of this function, for example, a system currently using an SH7708, with a 60 MHz CPU frequency and 30 MHz bus frequency, can be upgraded to a system with a 90 MHz CPU frequency and 30 MHz bus frequency simply by replacing the chip with an SH7708R, and without any other hardware modifications.

For the first-time the SH7718R offers support for floating-point operations in the SuperH series. Floating-point notation enables numeric values covering a wide dynamic range to be expressed with a high degree of precision. Recently, floating-point functions have become necessary in such areas as coordinate computation in graphics processing and equipment control requiring high precision. The floating-point operations provided in the SH7718R conform to IEEE-754 specifications. To enable high-speed floating-point processing to be provided at low cost, only single-precision floating- point operations are supported. All SH7718R floating-point operations except FDIV and FSQRT can be executed in one clock cycle, as can the multiply-and-accumulate operations (FMAC instruction) frequently used in graphics applications and signal processing, making it possible for the 100 MHz SH7718R to achieve a peak floating-point performance of 200 MFLOPS.

Apart from the CPU, on-chip functions include an MMU which is essential when using an operating system that supports memory protection and virtual memory, a 32-bit multiplier, 32-bit timer, real-time clock, serial communication interface (SCI), and an interface allowing direct connection of various kinds of memory, including PCMCIA cards and synchronous DRAM. The package is a 144-pin LQFP. The SH7708R and SH7718R feature full software compatibility with current SuperH series models, and pin compatibility with the SH 7708. Future developments in SH-3 series will continue on high- performance versions and versions with modified on-chip supporting functions, among others. Hitachi is also developing the SH-4, which will be a super-scalar CPU designed for a 300-MIPS performance level.

- Notes -
(1) SuperH is a trademark of Hitachi, Ltd.
(2) Windows is a registered trademark of Microsoft Corporation.

- Features -
1. High performance
High processing performance of 100 MIPS/100 MHz, ideal for portable information devices and multimedia products.
2. Floating-point support (SH7718R)
On-chip 200 MFLOP high-performance floating-point unit. Ideal for graphics application systems and control equipment requiring high precision.
3. On-chip power management functions
On-chip software-controllable power management functions offer fine control of power consumption, ideal for portable information devices. The ratios of the bus frequency, the CPU frequency, and the internal peripheral modules can be switched dynamically under program control by setting control registers. For example, an application could set the bus frequency to 25 MHz, and then switch the CPU operating frequency between 25, 50, 75, and 100 MHz, depending on the processing speed required by the program. At 25 MHz, although the processing speed is reduced, the power consumption is reduced proportionately. In addition, applications can also control module standby, which specifies individually the use or disabling of the MMU, cache, peripheral modules, and PLL circuit, standby mode, sleep mode, output of a clock for external bus control, and other aspects. Furthermore, the SH7708S and SH7718R include a 3x frequency multiplier for the CPU clock.
4. On-chip MMU
Support for operating systems handling memory protection and virtual memory. As the number and types of programs handled by microcontrollers increase, an operating system becomes indispensable for program control and protection. To support the operating system, the SH-3 series provides an on-chip MMU and supports privileged mode. This MMU provides address conversion (conversion from logical addresses to physical addresses) and memory protection in page units. The page size can be set to be either 1K byte or 4K bytes. The SH-3 has a large-capacity workstation/server class 128-entry TLB* so that TLB misses almost never occur. Furthermore, since address conversion occurs in parallel with cache searching, execution speed is not reduced by address conversion when a hit occurs. The SH-3 series also supports privileged mode operation so that the operating system can be isolated from user programs. By running the operating system in privileged mode and user programs in user mode, the operating system can efficiently manage user programs. An operating system can be designed so that other user programs and the operating system itself cannot be destroyed by a runaway user program.
5. Other features
* Pin-compatible with the SH7708 and software upward compatible with the earlier SuperH series
* High-speed interrupt/bank registers
* Support for direct interfacing to various kinds of memory (first-time on-chip implementation of a PCMCIA interface circuit)
* On-chip parallel shifter (for faster shift instructions)
* Comprehensive range of on-chip supporting functions (32-bit multiplier, real-time clock, 32-bit timer )
* TLB (translation lookaside buffer): A cache that records the logical address and the physical address as a pair each time a logical to physical address conversion occurs. Since the SH-3 TLB includes 128 entries, it can record logical/physical address for 128 pages. There is no reduction in execution speed for address conversion for logical/physical address pairs present in the TLB.

- Application Product Examples -
- Information and OA equipment
Portable information devices, Handheld PCs, LBPs, fax/modems, file control
- Consumer products
Amusement equipment such as game machines, multimedia products, set-top boxes
- Industrial/automotive
FA/robots, car navigation systems, measuring instruments

- Pricing in Japan -

Catalog No	Price per 10,000 unit lot (yen/unit)
SH7708R (HD6417708R)	2,200
SH7718R (HD6417718R)	2,500

- Specifications -

Main Specifications of SH7708R

Item	Specification
Power supply voltage	3.3 V
Operating frequency	100 MHz
Processing speed	100 MIPS/100 MHz
Power dissipation	550 mW (typ.)
Cache configuration	8 kB, mixed instructions/data, 4-way set- associative, write-through/write-back selectable, LRU system
CPU	SH-3
On-chip supporting functions	MMU, one serial channel, 3 timer channels, real-time clock, 8-bit I/O port, memory interface (DRAM/SRAM / synchronous DRAM/burst ROM/PCMCIA), 32-bit multiplier, etc.
Bus width	16/32 bits selectable
Package	144-pin LQFP (0.5 mm pitch, 20 mm x 20 mm)
Process	0.35-micron 3-layer aluminum CMOS process

Main Specifications of SH7718R

Item	Specification
Power supply voltage	3.3 V
Operating frequency	100 MHz
Processing speed	100 MIPS/100 MHz, 200 MFLOPS/100 MHz (peak) Power dissipation 600 mW (typ.)
Cache configuration	8 kB, mixed instructions/data, 4-way set-associative, write-through/write-back selectable, LRU system
CPU	SH-3E (Upward compatible with SH-3) IEEE-754-compliant single-precision floating-point instructions
On-chip supporting functions	MMU, one serial channel, 3 timer channels, real-time clock, 8-bit I/O port, memory interface (DRAM/SRAM / synchronous DRAM/burst ROM/PCMCIA), 32-bit multiplier, etc.
Bus width	16/32 bits selectable
Package	144-pin LQFP (0.5 mm pitch, 20 mm x 20 mm)
Process	0.35-micron 3-layer aluminum CMOS process

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