June 8, 1998
Hitachi Releases High-performance (37 MIPS) 32-bit
SuperH RISC Microcontroller
|
Notes: | 1. | SuperH is a trademark of Hitachi, Ltd. |
2. | F-ZTAT is a trademark of Hitachi, Ltd. |
Application Product Examples
[Industrial and Automotive]
In-car navigation systems, Motor control, Test equipment, Terminals, Factory automation equipment, Sequencers, Numerical control
[Consumer]
Wide-screen TV, Multimedia equipment, Electronic musical instruments
[Information and OA Equipment]
Facsimile units, Digital plain-paper copiers, Printers, Hard disk drives, Multi-function printers, Scanners
Pricing in Japan
Catalog No. | Operating voltage | Operating frequency | Sample price (Yen) | |
SH7017F | HD64F7017F28 | 5V +/- 0.5V | 28.7MHz | 4,000 |
SH7016 | HD6437016F28 | 5V +/- 0.5V | 28.7MHz | 3,000 |
Features
This new product is fabricated in a 0.6-micrometer two metal layer CMOS process and is based on the SH-2 CPU core, which includes a 32-bit DSP functional unit. When operating at 5 V, it can achieve a performance of 37 MIPS. As such, it can provide high-speed processing appropriate for applications such as multimedia equipment and high-performance industrial equipment.
1. Single-voltage flash memory
The SH7017F allows the microcontroller programs and control data to be rewritten with the device onboard in the application in all stages of the product cycle,
from development through test sample production and
mass production ramp up to full-scale mass production.
Also, since the SH7017F includes a voltage step-up
circuit, the flash memory data can be rewritten without providing a separate flash memory data read/write power supply (e.g. 12 V) thus easing power supply design
in applications.
2. Single-chip microcontroller that includes both
flash memory and cache memory
The SH7017F includes both 128 kB of high-speed single- voltage flash memory that allows single cycle instruction access and a 1 kB direct mapped instruction cache. The flash memory allows the majority of programs that were previously executed from external memory to
be stored in flash memory, thus resulting in a significant
increase in the execution performance of large-scale
programs. Additionally, the internal 1 kB instruction cache increases the instruction execution speed of programs that can not be stored in internal ROM. Therefore, as compared to the SH7034 single-chip microcontroller based on the SH-1 core, the percentage of instructions in the whole program that can be executed in a single cycle is increased significantly due to the combined effect of the internal ROM and the cache memory. Furthermore, the high clock frequency
means that the CPU processing capability is significantly increased, even at the system level.
3. Powerful peripheral functions
The SH7017F includes an extensive set of peripheral functions, include DMAC, timers, serial I/O,
an A/D converter, and direct connection of external memory. These can contribute to miniaturization and reduced
costs in end products. Note that the A/D converter and other functions have been improved over those included in, for example, the SH7034.
Development Environment
The following software and hardware are available as a development environment for the SH7017F and SH7016.
Software: C cross compiler, cross assembler, cross simulator/debugger | Hardware: Real-time emulator (E7000) |
Specifications
Item | Specifications | |
Power-supply voltage | 5V +/- 0.5V | |
Clock frequency | 28.7MHz | |
Performance | 37MIPS / 28.7MHz | |
CPU core | 32-bit Hitachi-original RISC processor : SH-2 core | |
Number of CPU instructions | 62 instructions (All instructions are 16-bit fixed-length instructions.) | |
DSP | functions 32 bits x 32 bits -> 64 bits | : 2 to 4 cycles |
32 bits x 32 bits + 64 bits ->64 bits | : 2 to 4 cycles | |
16 bits x 16 bits ->32 bits | : 1 to 3 cycles | |
16 bits x 16 bits +64 bits ->64 bits | : 2 or 3 cycles | |
Internal flash memory | 128 kB F-ZTAT version (32 bits can be accessed in a single clock cycle.) Single-voltage power supply, erase and rewrite supported. (SH7017F) | |
Internal ROM | 64 kB mask ROM (32 bits can be accessed in a single clock cycle.) (SH7016) | |
Internal RAM | 4 kB (SH7017F) 3 kB (SH7016) | |
Internal Cache | 1 kB instruction cache (direct mapped) | |
Of the internal RAM, 2 kB is shared with the cache (1 kB is used as the address array, 1 kB is used as the data array) | ||
External memory | SRAM and DRAM can be connected directly using the built-in bus state controller. | |
Four SRAM areas (4 MB each) and one DRAM area (16 MB) | ||
Supports idle cycle insertion to prevent bus collisions. | ||
Data bus width: 16 bits (external) | ||
Internal peripheral functions | DMAC x 2ch | |
Multifunction timer pulse unit (MTU) ... Provides three multifunction timers. | ||
Eight-input 10-bit resolution A/D converter | ||
Two serial communications interface (SCI) channels | ||
Two compare/match timers | ||
Interrupt controller (INTC) | ||
Parallel I/O ports | ||
Watchdog timer (WDT) | ||
Clock oscillator (CPG): On-chip clock multiplier PLL | ||
Package | 112-pin QFP (lead pitch: 0.65 mm, 20 mm x 20 mm) | |
Power dissipation | 5 V, 700 mW (typical) at 28.7 MHz | |
Fabrication process | 0.6-micrometer two layer metal CMOS process |
Internal Memory Organization
SH7016 | SH7017F | |
RAM | 3 kB (1 kB)* | 4 kB (2 kB)* |
Cache | 1 kB | 1 kB |
ROM/flash memory | 64 kB (Mask ROM only) | 128 kB |
Note * Values in parentheses apply when the cache is used.