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News Release
October 1, 1998

Hitachi Releases 64-Mbit Synchronous DRAMs Using DDR system for High-Speed Data Transfer

- 266 Mbps per pin; for use as main memory and expansion memory in high-end personal computers, workstations, etc. -

Hitachi, Ltd.(NYSE:HIT) today announced the release of the HM5464401DTT series (x4-bit configuration), HM5464801DTT series (x8-bit configuration), and HM5464161DTT series (x16-bit configuration) 64-Mbit synchronous DRAMs using the DDR (Double Data Rate) system (DDR SDRAMs), offering a high-speed data transfer rate of 266 Mbps per pin*1, for use as main memory, image memory, and cache memory in high-end personal computers, workstations, servers, etc. Sample shipments will begin in November 1998 in Japan.

These new products employ the DDR system in which data input/output is synchronized with the rise and fall of an external clock, enabling a data transfer rate of 266 Mbps per pin (with a 133 MHz clock frequency) to be achieved, twice the rate of ordinary synchronous DRAM. A JEDEC (Joint Electron Device Engineering Council) standard 66-pin, 400 mil*2 TSOP-II package is used.

With the dramatic increase in system speed and CPU performance in personal computers, workstations, and similar equipment, there is a demand for higher transfer rates for the DRAMs used as main memory, image memory, and cache memory, to enable large quantities of data to be processed at high speed. Against this backdrop, Hitachi has developed 64-Mbit DDR SDRAMs as high-speed DRAMs for the next generation of machines.

The HM5464401DTT series, HM5464801DTT series, and HM 5464161DTT series employ a 0.25 micrometers process, witha x4-bit, x8-bit, and x16-bit configuration, respectively. These devices operate in synchronization with an external clock, but data input/output is synchronized with both the rising and falling edges of the clock, enabling data to be transferred at twice the clock frequency.

The operating frequencies of these products are 83 MHz, 100 MHz, 125 MHz, and 133 MHz enabling data rates of 166 Mbps/pin, 200 Mbps/pin, 250 Mbps/pin, and 266 Mbps/pin (twice the clock rate) to be achieved. These new synchronous DRAMs use an SSTL-2*3 interface to provide high-speed operation, and a 2.5 V power supply voltage for high speed and low power consumption. Devices offering even higher speeds and larger capacities are planned for the future.

Notes:
1.bps: Bits per second (the number of bits that can be transmitted in one second)
2.mil: 100 mil = 2.54 mm
3.SSTL: Stub Series Terminated Logic

Typical Applications
Main memory and expansion memory in high-end workstations, servers, etc.
On-board memory in high-end personal computers
Buffer memory for image processing
High-speed DRAM cache memory

Prices in Japan
Product Code Operating frequency Configuration Sample Price (Yen)
HM5464401DTT-12 83 MHz 4M x 4 x 4banks 2,000
HM5464401DTT-10 100 MHz 4M x 4 x 4banks 2,000
HM5464401DTT-8 125 MHz 4M x 4 x 4banks 2,000
HM5464401DTT-7H 133 MHz 4M x 4 x 4banks 3,000
HM5464801DTT-12 83 MHz 2M x 8 x 4banks 2,000
HM5464801DTT-10 100 MHz 2M x 8 x 4banks 2,000
HM5464801DTT-8 125 MHz 2M x 8 x 4banks 2,000
HM5464801DTT-7H 133 MHz 2M x 8 x 4banks 3,000
HM5464161DTT-12 83 MHz 1M x 16 x 4banks 2,000
HM5464161DTT-10 100 MHz 1M x 16 x 4banks 2,000
HM5464161DTT-8 125 MHz 1M x 16 x 4banks 2,000
HM5464161DTT-7H 133 MHz 1M x 16 x 4banks 3,000

Specifications
Item HM5464401DTT HM5464801DTT HM5464161DTT
Product configuration 4M x 4 x 4banks 2M x 8 x 4banks 1M x 16 x 4banks
Power supply voltage 2.5 V
Operating frequency 83 MHz/100 MHz/125 MHz/133 MHz
Data transfer rate 166 Mbps/pin, 200 Mbps/pin, 250 Mbps/pin , 266 Mbps/pin
Burst length 2/4/8
Burst sequence Sequential/interleaved
CAS latency 2/2.5
Refreshing 4096 cycles/64 ms
Package 400-mil 66pin plastic TSOP-II
Process 0.25 micrometers CMOS
  

    
WRITTEN BY Secretary's Office
All Rights Reserved, Copyright (C) 1998, Hitachi, Ltd.