Hiroyuki Mizuno received the M.S. (Semiconductor Physics) and Ph.D. (Eng.) (Integrated Circuits) degrees in electronic engineering from Osaka University, Osaka, Japan, in 1993, and 2001, respectively. In 1993 he joined the Central Research Laboratory, Hitachi, Ltd., Tokyo, Japan, where he has been engaged in the research and development of high-speed and low-power semiconductor circuits for SRAMs, microprocessors (SuperH) and system-on-a-chip (SH-Mobile). He was a visiting scholar at the Department of Computer Science, Stanford University from 2002 to 2003. Since 2009, he has extended his research interests to information technology. In 2011, he launched a new generation computing project at Hitachi which led to the development of quantum-inspired computing (CMOS Annealing). His current research interests include quantum computers as well as AI through interdisciplinary approach and Cyber Physical and Human System that aims to balance the three pillars of social, environmental and economic values. He has held his current position since 2025. He is a Fellow of the Institute of Electrical and Electronics Engineers (IEEE) and a member of the Association for Computing Machinery (ACM).
Group leader of the RInCA R&D Project, “Practical examination of ELSI on smartization of community through four-dimensional co-creation (PM of Prof. Y. Deguchi, Kyoto University),” Japan Science and Technology Agency (JST), 2022 – present.
Project manager of The Moonshot R&D Program, “Large-Scale Silicon Quantum Computer Project,” Japan Science and Technology Agency (JST), 2020 – present.
Industry promotion committee member, IEEE Japan Council, 2019 - 2023.
Operation and evaluation committee member, “Macroscopic Quantum Machines,” The ERATO research funding program, Japan Science and Technology Agency (JST), 2019 – 2022.
Industry strategy committee member, Semiconductor Industry Research Institute Japan (SIRIJ), 2011 – 2014.
Technical program committee member (Emerging Technologies and Applications), Session chair/co-chair, IEEE Asian Solid-State Circuit Conference (A-SSCC), 2007 – 2010.
Technical program committee member (Technology Directions), Session chair/co-chair, IEEE International Solid-State Circuits Conference (ISSCC), 2004 – 2007.
Forum committee member (Design of 3D-Chipstacks), IEEE International Solid-State Circuits Conference (ISSCC), 2007
Technical program committee member (Technology & Digital Circuits), IEEE International Symposium on Low Power Electronics and Design (ISLPED), 2003.
Major awards
Plenary talk, “Quantum Computing from Hype to Game Changer,” IEEE Symposium on VLSI Technology and Circuits, 2023.
SSDM2022 Paper Award, “16×8 Quantum Dot Array Operation at Cryogenic Temperatures,” JSAP International Conference on Solid State Devices and Materials, 2022.
IEEE SSCS Japan Industry Contribution Award, 2020.
LSI of the Year 2008 Semi Grand Prix, “Multi-core LSI with Independent Power-off Control of 8 CPUs and 8 RAMs,” The Semiconductor Industry News, 2008.
Telecommunication System Technology Award, “A Noise Immune GHz Clock Distribution Scheme Using Synchronous Distributed Oscillators,” The Telecommunications Advancement Foundation, 2008.
The Takeda Techno-Entrepreneurship Award 2001, “Low Power Circuit Technology of Microcontrollers,” The Takeda Foundation, 2001.
R&D 100 Award, “SH-4 (SH7750) Series Microprocessor,” R&D Magazine, 1999.
Ichimura Industrial Award, “Development and Commercialization of Low-power Microprocessor SuperH Series for Consumer and Information Appliances,” The New Technology Development Foundation, 1998.
Nikkei BP Technology Award, “Development of SuperH RISC Engine Series for Consumer Multimedia Products,” Nikkei Business Publications, Inc., 1996.
